Aion Silicon

Principal Engineer – SoC Physical Design & Chip-Level Implementation

Maroc

CDI / Temps pleinHybrideIngénieur / École d'ingénieursAnglaisInformatique / IngénierieInformatique / IT

L’essentiel du poste

Résumé par Postule AI

Principal Engineer role leading complex ASIC/SoC physical design implementation from architecture through tape-out. Requires 15+ years of experience in full-chip physical design, advanced-node technology (5nm and below), and proven leadership of multiple successful SoC tape-outs. Hands-on technical expert responsible for floorplanning, power integrity, timing closure, and cross-functional coordination with architecture, verification, and silicon validation teams.

Vos missions

  • Lead full-chip physical implementation including floorplanning, power planning, clock implementation, place-and-route, timing closure, and signoff
  • Drive physical design methodologies, best-known methods, and implementation guidelines across projects
  • Coordinate physical design execution across block, subsystem, and top-level implementation teams
  • Define project milestones, manage dependencies, and drive execution to meet tape-out schedules
  • Collaborate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams
  • Debug and resolve design, flow, and methodology issues with scalable solutions

Profil recherché

  • You have 15+ years of proven ASIC/SoC physical design experience with multiple successful tape-outs
  • You are comfortable working with advanced technology nodes (5nm and below) and large-scale designs
  • You excel at cross-functional collaboration and can lead geographically distributed engineering teams
  • You have deep expertise in both Synopsys and Cadence EDA tools and scripting languages
  • You are a hands-on technical leader who enjoys solving complex physical design challenges

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About the Role

We are seeking a highly motivated and experienced Principal Engineer to lead the implementation of complex ASIC/SoC designs from architecture definition through successful tape-out. The ideal candidate will have deep expertise in full-chip physical design, SoC integration, advanced-node implementation, and cross-functional technical leadership.

This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, RTL, Verification, DFT, STA, Package, and Silicon Validation teams.

Key Responsibilities

  • Partner with Front-End and Architecture teams to understand chip architecture and drive physical design considerations early in the development cycle
  • Lead full-chip physical implementation activities including floorplanning, power planning, clock implementation, place-and-route, timing closure, and signoff
  • Drive physical design methodologies, best-known methods (BKMs), checklists, and implementation guidelines across projects
  • Serve as the technical focal point for physical design execution and coordinate activities across block, subsystem, and top-level implementation teams
  • Define project milestones, track progress, manage dependencies, and drive execution to meet tape-out schedules
  • Collaborate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to achieve project goals

Required Qualifications

  • B.Tech or M.Tech in Electrical Engineering, Electronics, Computer Engineering, or related discipline
  • 15+ years of ASIC/SoC Physical Design experience with proven track record of multiple successful tape-outs
  • Strong understanding of ASIC/SoC integration including floorplanning, clock distribution, power distribution networks, and hard IP integration
  • Hands-on experience with large-scale SoCs exceeding 20M gates operating at frequencies greater than 1GHz
  • Experience in advanced technology nodes including 22nm, 16nm, 7nm, 5nm, and below
  • Strong leadership skills with ability to drive execution across geographically distributed teams

Tools & Technical Skills

  • Synopsys: Fusion Compiler (FC), ICC2, PrimeTime (PT), StarRC, PrimePower
  • Cadence: Innovus, Tempus, Voltus, Quantus
  • Physical Verification: Calibre, IC Validator (ICV), Pegasus
  • Scripting & Automation: TCL, Perl, Python, Shell scripting

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