Indie Semiconductor

Senior Digital DFT Engineer

Rabat

CDI / Temps pleinSur siteMaster / Bac+5AnglaisInformatique / IngénierieInformatique / IT

L’essentiel du poste

Résumé par Postule AI

Senior Digital DFT Engineer position at indie Semiconductor in Rabat, Morocco. Lead pre-silicon DFT insertion, verification, and ATE test program development for automotive and sensing semiconductor designs. Requires 3+ years DFT experience, MS in Electrical/Computer Engineering, and expertise in scan techniques, LBIST, MBIST, and fault modeling. Reports to Digital IC Design DFT Manager.

Vos missions

  • Define DFT requirements and architecture based on project specifications and IP content
  • Implement and verify standard DFT techniques including Scan, LBIST, MBIST, and Boundary Scan
  • Collaborate with Analog and Mixed Signal designers to develop custom test logic for IP testing
  • Analyze test coverage and generate ATE test patterns including custom patterns for improved coverage
  • Support post-silicon ATE test program bring-up and test time reduction

Profil recherché

  • You have 3+ years of proven DFT implementation and verification experience in semiconductor design
  • You are passionate about automotive and sensing technology with strong functional safety knowledge
  • You excel at cross-functional collaboration with analog, mixed-signal, and test engineering teams
  • You have deep expertise in scan techniques, LBIST, MBIST, and fault modeling methodologies

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About the Role

indie Semiconductor seeks a Senior DFT Engineer in Rabat, Morocco to execute all aspects of pre-silicon DFT insertion and verification. You will interface with the test engineering team for ATE test program development and silicon bring-up, joining a team creating cutting-edge designs in ADAS, Sensing Systems, Power Management, High Speed converters, and Wireless connectivity.

Main Responsibilities

  • Define DFT requirements and architecture based on project specifications and IP content
  • Implement and verify standard DFT techniques including Scan, LBIST, MBIST, and Boundary Scan
  • Collaborate with Analog and Mixed Signal designers to define and implement custom test logic for effective IP testing
  • Analyze chip and block test coverage and generate test patterns for ATE
  • Generate custom test patterns for IPs and functional tests to improve coverage and screen test escapes
  • Support post-silicon ATE test program bring-up and test time reduction

Required Qualifications

  • 3+ years industry experience implementing and verifying DFT/DFD techniques for digital and mixed signal designs
  • Strong fundamental knowledge of DFT, core-based test methodology, and scan isolation
  • Understanding of fault models: Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware
  • Knowledge of JTAG, Scan Compression, ATPG, Fault Simulation, at-speed testing, and MBIST
  • Experience with self-testing techniques (LBIST and MBIST) for automotive functional safety
  • Familiarity with System Verilog
  • MS degree in Electrical and/or Computer Engineering
  • Fluent English (written and spoken) with excellent communication skills

Preferred Skills

  • Knowledge of test methodologies for mixed signal IPs (ADC, DAC, Serdes)
  • Familiarity with UVM and use of assertions during verification

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